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d ata s heet 10-gbps gaas family high-speed optical communications system april 1999 o k i g a a s p r o d u c t s
n n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC oki semiconductor contents 10-ghz gaas family .........................................................................................................................1 KGL4201 10-ghz 8:1 multiplexer ......................................................................................................... .................... 3 kgl4202 10-ghz 1:8 demultiplexer ...................................................................................................... .................. 7 ghdd4411 ex-or circuit.................................................................................................................. ........................ 11 ghdd4414 decision circuit with phase detector ........................................................................................... ........... 15
1 oki semiconductor 10-ghz gaas family high-speed optical communications systems introduction okis 10-ghz logic devices are manufactured using a 0.2-m, ion-implanted process, which is similar to okis familiar 0.5-m telecommunications process. however, the 0.2-m process uses a phase-shifting edge line (pel) masking method for gate fabrication. gold-based, three-level metal interconnections are used for high density and shorter wiring paths. layers 1 and 2 are signal lines. layer 3, which is formed by electroplating, is used for ground or power supply lines because of its lower resistance. an optional buried p channel structure is adopted for reducing short channel effects. the following table shows the digital gaas logic processes of the 10-ghz gaas family. the key to operating reliably at 10 gbps is logic circuitry that can easily manipulate data at over 13 gbps. the higher frequency overhead is required to meet the different clock skews encountered when design- ing and routing 10-gbps data management hardware. the logic is either direct-coupled fet logic (dcfl) or source-coupled fet logic (scfl). the low-drive disadvantage of dcfl can be improved by using super-buffer fet logic (sbfl). the basic speed of sbfl is slower than dcfl, but sbfl is faster with higher fanouts and longer metal runs. a designer selects the best performing logic for each logic element application. sbfls used for clock distribution, output buff- ers, etc. typical gate delays of 9 ps and power of 2 mw per gate are achieved. register logic elements like d-flip flops are assembled using memory cell flip flops (mcff) as shown in figure 1 .the operation speed of a mcff, which is about twice that of a conventional 6 nor-gate circuit, operates at very low power. to simplify device interconnections, ac-coupled clock and data input lines are created using the circuit shown in figure 2 . features gaas logic processes basic fet process basic gate circuit photo masking gate length (m) ft (ghz) gate delays (ps) application mesfet dcfl or sbfl i-line printing 0.5 30 25 < 2.4 gbps standard cell mesfet dcfl or sbfl pel < 0.2 60 9 >12-gbps hand-routed logic pseudomorphic-inverted hemt dcfl or sbfl pel 0.2 > 60 7 > 20-gbps low-density logic pseudomorphic bp--mesfet analog deep uv 0.2 > 60 C analog amplifier ? 10-gbps operation: highest speed available ? ecl level logic swings: easy interface to other logic ? inputs internally terminated: reduces noise and phase jitter ? 50- w i/os: easy to interconnect hardware
n 10-ghz gaas family n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 2 oki semiconductor many 10-gbps inputs are self-biased and 50- w terminated, for capacitance coupling. the outputs are dc- coupled to drive 50- w ground terminated lines. data sheets this document contains data sheets for the KGL4201, kgl4202, ghdd4411, and ghdd4414 10-gbps gaas high-speed optical communication systems. data sheets for other communication devices may be obtained from the oki semiconductor web site, www.okisemi.com or from the local sales office. figure 1. memory cell flip-flops data data clock clock q q master slave master/slave flip-flop data clock clock out flip-flop figure 2. ac-coupled, self-biased logic input data or clock in 50 w reference dummy gate
3 oki semiconductor KGL4201 10-ghz 8:1 multiplexer general description okis KGL4201 is a 10-ghz 8:1 multiplexer designed to operate in 10-gbps communication links. this circuit synchronously merges eight 1.25-gbps data streams, clocked at low frequency rates into a single 10-gbps stream, clocked at the higher frequency. in the KGL4201 multiplexer, the 10-ghz master clock is first divided by two, then by four. the lower frequency components are first multiplexed by four, then the two groups are merged into a single data stream using the master 10-gbps clock. complementary 1/8 synchronous clock outputs are made available from the KGL4201 for use in synchronizing lower fre- quency logic. all signal interfaces are 50- w with direct dc coupling on the 1.25-gbps data inputs and phase-locked 1.25-gbps clock outputs. the 10-gbps data output and 10-ghz clock input are ac-capacitively-coupled for ease of interfacing at microwave speeds and reducing ground noise induced phase jitter. all package clock and data pins are separated by either ground or supply voltage pins to control the i/o impedance, maintain signal isolation and reduce phase noise. the KGL4201 is shipped in a 40-pin ceramic flat-package with impedance-controlling ground plane and flush mounting bottom heat sink. features ? ac-coupled 10 gbps i/o: eliminates dc coupled phase jitter ? 1/8 clock generated on chip: easy to synchronize downstream logic ? 2 v, 2.4 w ? isolated i/o pins: minimize noise and impedance variation ? packaged in 40-pin ceramic flat-package with ground plane and heat sink.
n KGL4201 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 4 oki semiconductor 1 10 20 31 11 21 30 40 11.0 sq 13.01 sq 14.84 sq 1.27 2 0.3 0.4 0.05 1.7 0.15 0.7 0.05 0.9 .005 pin configuration block diagram pin configuration pin name pin pin name pin pin name pin pin name 1 gnd 11 gnd 21 vdd 31 gnd 2 q 12 vdd 22 gnd 32 vdd 3 gnd 13 d0 23 gnd 33 d7 4q 14 gnd 24 ck 34 gnd 5 gnd 15 d2 25 gnd 35 d5 6 gnd 16 d4 26 gnd 36 d3 7 1/8ck 17 gnd 27 rck 37 gnd 8 gnd 18 d6 28 gnd 38 d1 9 1/8ck 19 gnd 29 gnd 39 vb 10 vb 20 gnd 30 gnd 40 vdd 1 10 20 31 11 21 30 40 10.67 sq 11.43 sq 13.01 sq 14.84 sq 1.27 2 0.3 0.125 0.05 0.4 0.05 1.7 0.15 0.7 0.05 0.9 .005 d0 d2 d4 d6 d1 d3 d5 d7 4:1 mux 1/8ck 1/8ck 4:1 mux 2:1 mux output latch q q delay delay 1/2 divider 1/4 divider ck
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n KGL4201 n 5 oki semiconductor electrical characteristics recommended operating conditions parameter symbol rated value unit min typ max power supply voltage for internal logic v dd 1.9 2.0 2.1 v power supply voltage for output buffer v b 1.9 2.0 2.1 v operating temperature range at package base t s 0 C 70 c dc characteristics v dd = 2v 0.1v, vb=2v 0.1v ts = 0 to 70c parameter symbol test condition rated value unit min. typ. max. power dissipation p C 2.4 3.0 w high-level 1/8 ck output voltage v oh 0.85 1.3 v low-level 1/8 ck output voltage v ol 0 0.3 v data output voltage swing v od 50- w load 0.7 1.2 v p-p clock input voltage swing v ck capacitive coupling 0.5 0.9 v p-p high-level data input voltage v idh 0.8 1.3 v low-level data input voltage v idl 0 0.3 v ac characteristics v dd = 2v 0.1v, vb=2v 0.1v ts = 0 to 70c parameter symbol test condition rated value unit min. typ. max. minimum clock period d t c C C 100 ps setup time (data to 1/8 ck )t ps 450 500 550 ps hold time (1/8 ck to data) t dh -400 -350 -300 ps ck-d[7:0] phase margin d t m input clock period is 100 ps 550 650 ps rise time (q, q )t r 20 30 40 ps fall time (q, q )t f 20 30 40 ps
n KGL4201 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 6 oki semiconductor interface timing ck d0 d1 d2 d3 d4 d5 d6 d7 q a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 d1 d2 d3 d4 e1 e2 e3 e4 f1 f2 f3 f4 g1 g2 g3 g4 h1 h2 h3 h4 h1 g1 f1 e1 d1 c1 b1 a1 h2 g2 f2 e2 d2 c2 b2 a2 c3 b3 a3 q h1 g1 f1 e1 d1 c1 b1 a1 h2 g2 f2 e2 d2 c2 b2 a2 c3 b3 a3 1/8 ck 1/8 ck
7 oki semiconductor kgl4202 10-ghz 1:8 demultiplexer general description okis kgl4202 is a 10-ghz 1:8 demultiplexer designed to operate in 10-gbps communication links. this circuit synchronously separates a single 10-gbps data stream, clocked at up to 10 ghz, into eight lower frequency data streams, clocked at lower frequency rates. in the kgl4202 demultiplexer, the 10-ghz master clock is first divided by two, then by four. the 10-gbps data stream is first divided into two syn- chronous serial paths, then these two data streams are separated into four each lower speed data streams and brought out to data latched outputs. complementary 1/8 synchronous clock outputs are made avail- able from the kgl4202 for use in synchronizing lower frequency logic. all signal interfaces are 50 w with all inputs internally terminated in 50 w . direct dc coupling is used on the 10-gbps data input, the 1.25-gbps data outputs and phase-locked 1.25-gbps clock outputs. the 10- ghz clock input is ac-capacitively-coupled for ease of interfacing at microwave speeds and reducing ground noise induced phase jitter. the package 10-ghz clock and 10-gbps data pins are separated by ground pins to control the i/o impedance, maintain signal isolation and reduce phase noise. the eight data outputs are distributed to opposite sides of the package to facilitate hardware layout and reduce noise. over one third of the chip power is due to the ten 50- w outputs. the kgl4202 is shipped in a 40-pin ceramic flat-package with impedance-controlling ground plane and flush-mounting bottom heat sink. features ? ac-coupled 10 gbps i/o: eliminates dc coupled phase jitter ? 1/8 clock generated on chip: easy to synchronize downstream logic ? isolated i/o pins: minimizes noise and impedance variation ? 2 v, 3.2 w ? packaged in 40-pin ceramic flat-package with ground plane and heat sink
n kgl4202 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 8 oki semiconductor pin configuration block diagram pin configuration pin name pin pin name pin pin name pin pin name 1 gnd 11 gnd 21 vdd 31 gnd 2 1/8ck 12 vdd 22 gnd 32 vdd 3 gnd 13 q1 23 gnd 33 q6 4 1/8ck 14 gnd 24 ckin 34 gnd 5 rd 15 q3 25 gnd 35 q4 6 gnd 16 q5 26 gnd 36 q2 7 n.c. 17 gnd 27 rck 37 gnd 8 gnd 18 q7 28 gnd 38 q0 9 gnd 19 vb 29 gnd 39 vb 10 vb 20 gnd 30 vb 40 vdd 1 10 20 31 11 21 30 40 10.67 sq 11.43 sq 13.01 sq 14.84 sq 1.27 2 0.3 0.125 0.05 0.4 0.05 1.7 0.15 0.7 0.05 0.9 .005 1:4 demux 1/8ck 1/8ck 1:4 demux 1:2 demux q0 delay 1/2 divider 1/4 divider d ck q2 q4 q6 q1 q3 q5 q7 1/8ck 1/8ck
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n kgl4202 n 9 oki semiconductor electrical characteristics absolute maximum ratings parameter symbol rated value unit min. max. supply voltage for internal logic v dd -0.3 2.3 v supply voltage for output buffer v b -0.3 2.3 v clock input ck -0.3 1.5 v data inputs d -0.3 1.5 v temperature at package base under bias t s -45 100 c storage temperature t st -45 125 c recommended operating conditions parameter symbol rated value unit min. typ. max. power supply voltage for internal logic v dd 1.9 2.0 2.1 v power supply voltage for output buffer v b 1.9 2.0 2.1 v operating temperature range at package base t s 0 C 70 c dc characteristics v dd = 2 v 0.1 v, vb=2 v 0.1 v t s = 0 to 70c parameter symbol test condition rated value unit min. typ. max. power dissipation p 3.2 4.0 w high-level 1/8ck output voltage v oh 50- w load 0.85 1.3 v low-level 1/8ck output voltage v ol 50- w load 0 0.3 v data input voltage swing v id capacitive coupling 0.5 0.9 v p-p clock input voltage swing v ick capacitive coupling 0.5 0.9 v p-p ac characteristics v dd = 2v 0.1v, vb=2v 0.1v ts = 0 to 70c parameter symbol test condition rated value unit min. typ. max. minimum clock period d t c 100 ps setup time (d to ck )t ds -55 -45 -35 ps hold time (ck to d) t dh 70 80 90 ps ck-d phase margin d t m input clock period is 100 ps 50 65 ps 1/8ck - to valid data delay t c8q -40 -10 20 ps
n kgl4202 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 10 oki semiconductor interface timing timing ck q0 q1 q2 q3 q4 q5 q6 q7 d a1 a2 a3 b1 b2 b3 c1 c2 c3 d1 d2 d3 e1 e2 e3 f1 f2 f3 g1 g2 g3 h1 h2 h3 h1 g1 f1 e1 d1 c1 b1 a1 h2 g2 f2 e2 d2 c2 b2 a2 1/8 ck 1/8 ck h3 g3 f3 e3 d3 c3 b3 a3 d4 c4 b4 a4 ck d 1/8 ck 1/8 ck q[7:0] valid valid t c8q d t m t dh t ds d t c
11 oki semiconductor ghdd4411 ex-or circuit general description okis ghdd4411 is a 10-ghz exclusive-or/nor circuit designed to function in 10-gbps high-speed communication serial bit streams. the ex-or must operate from both rising and falling edges at an equivalent speed of 20-gbps non-return-to-zero (nrz) signal to extract a 10-gbps clock from a 10-gbps signal. using closely matched gilbert cell circuitry, this device operates at over 10 gbps using dcfl and sbfl logic from inverted hemt technology. internal input 50- w terminations and a self-referencing bias voltage allow capacitive coupling, simplifying interconnections. the ghdd4411 ex-or circuit is high-speed in a 28-pin ceramic flat package with impedance-controlling ground plane and flush-mounting bottom heat sink. features ? ex-or and ex-nor: outputs optimized for performance ? 1.5 v, 0.6 w: lowest power with 50- w interfaces ? packaged in 28-pin ceramic flat package with ground plane and heat sink
n ghdd4411 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 12 oki semiconductor pin configuration pin signal function pin signal function 1 in1bs input 1 bias input 15 vb power supply (buffer) 2 n.c. no connect 16 n.c. no connect 3 in1rf input 1 bias reference output 17 in2rf input 2 bias reference output 4 n.c. no connect 18 n.c. no connect 5 vb power supply (buffer) 19 in2bs input 2 bias input 6 gnd ground 20 gnd ground 7 exor ex-or output 21 in2 data input 2 8 gnd ground 22 gnd ground 9 n.c. no connect 23 vd power supply (logic circuit) 10 n.c. no connect 24 n.c. no connect 11 n.c. no connect 25 vd power supply (logic circuit) 12 gnd ground 26 gnd ground 13 exnor ex-nor output 27 in1 data input 1 14 gnd ground 28 gnd ground 0.3 10.16 14 6 20 28 0.125 2 15 8 0.5 9.6 0.5 0.5 6 0.1 2.1 0.1 7 8.6 9 12 0.1 11 12 16 0.1 1.27 dimensions in mm 2 1 5 19 15
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ghdd4411 n 13 oki semiconductor block diagram in1 in1 bs in2 in2 bs exnor exor in1 rf in2 rf
n ghdd4411 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 14 oki semiconductor electrical characteristics output waveform absolute maximum ratings parameter symbol min max unit suuply voltage for internal logic v dd -0.3 2.3 v supply voltage for outpu buffer v b -0.3 2.3 v clock input ck -0.3 1.0 v data input d -0.3 1.0 v temperature at package base under bias t s -45 100 c storage temperature t st -45 125 c recommended operating conditions parameter symbol min. typ. max. unit suuply voltage for internal logic v dd 1.4 1.5 1.6 v supply voltage for output buffer v b 1.4 1.5 1.6 v operating temperature range at package base t s 070c v dd = 1.5 v 0.1, v b = 1.5 v 0.1, t s = 0 to 70 c parameter symbol condition min. typ. max. unit power dissipation p 0.6 w input bit rate b 10 gb/s data input voltage amplitude v id capacitive coupling 0.2 0.8 v p-p data output voltage amplitude v od 50- w load, capacitive coupling 0.7 v p-p data output rise/fall time t 20 ps i63a-7, dec12,5-7, 25c, p horizontal - 20ps/div, vertical - 200 mv/div
15 oki semiconductor ghdd4414 decision circuit with phase detectors general description okis ghdd4414 is a 10-ghz decision circuit designed to strip data from high-speed serial bit streams in 10-gbps communication links. using a clock input at up to 10 ghz and using d-flip-flops, ex-ors, and phase detectors, this circuit separates a 10-gbps data stream into: clock output, data output, phase variation output, and data density output. a 10-ghz master clock drives two d-flip-flops in this circuit. buffered input data is clocked through the first flip-flop, then the second, data out is taken from the first flip-flop. the data input buffer is com- posed of a series of inverters to delay the signal and obtain a small decision ambiguity. a phase compar- ison is made of the buffered data and data from flip-flop one; a second phase comparison is made of the output of flip-flops one and two. the phase detectors are modified ex-or circuits with resistor summing of the logic gates to permit analog measurement of their outputs. any change in the timing relationships between the clock and data is seen at the output of the first phase detector. the second flip-flop operates as a 1-bit shift register with fixed 360-deg phase shift. the second phase detector output depends only upon the transition density (speed of rise and fall transitions) of the input data signal. all signal interfaces are 50- w with all inputs internally terminated in 50 w . the 10-ghz clock and data inputs are ac capacitively-coupled for ease of interfacing at microwave speeds and reducing ground noise induced phase jitter. data and phase outputs are dc-coupled. features ? phase detectors on chip: verifies data integrity ? isolated 10-gbps input pins: minimizes noise and impedance variation ? 1.5 v, 1 w: lowest power with 50- w interfaces ? 28-pin ceramic flat package with impedance controlling ground plane and flush mount heat sink
n ghdd4414 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 16 oki semiconductor pin configuration pin signal function pin signal function 1c bs clock bias input 15 v b power supply (buffer) 2 nc 16 p1 phase detector output 3c mb clock output duty monitor 17 p2 phase detector ref. output 1 4 nc 18 p3 phase detector ref. output 2 5v b powr supply (buffer) 19 v d power supply (logic circuit) 6 gnd 20 gnd 7d out data output 21 d in data input 8 gnd 22 gnd 9nc 23d bs data bias input 10 nc 24 d rf data bias reference output 11 nc 25 v d power supply (logic circuit) 12 gnd 26 gnd 13 c out clock output 27 ck clock input 14 gnd 28 gnd 0.3 10.16 14 6 20 28 0.125 2 15 8 0.5 9.6 0.5 0.5 6 0.1 2.1 0.1 7 8.6 9 12 0.1 11 12 16 0.1 1.27 dimensions in mm 2 1 5 19 15
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ghdd4414 n 17 oki semiconductor block diagram application block diagram d q ck pd p 1 d out lpf c mb c bs pd d q pd p 2 p 3 phase detector d d bs d rf c out fiber input pin-pd & preamp agc amp delay recti?er filter phase shifter limiting amp decision circuit out clock
n ghdd4414 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 18 oki semiconductor electrical characteristics phase detector circuit v dd = 1.5 v 0.1 v, v b = 1.5 v 0.1 v, t s = 0 to 70c parameter symbol condition min. max. unit power dissipation p 1 w decision ambiguity v idec 10 gbps prbs: 2 15 -1 0.05 v p-p phase margin d q 250 degree data input voltage amplitude v id capacitive coupling 0.8 v p-p clock input voltage amplitude v ic 0.4 0.8 v p-p data output voltage amplitude v od 50 w load capacitive coupling 0.7 v p-p clock output voltage amplitude v oc 0.7 v p-p clock output duty cycle d tyc 40 60 % clock to data delay t cd 25 45 ps phase detection sensitivity d v q 10 gbps prbs: 2 15 -1 0.28 mv/degree phase detection characteristics (d in amplitude = 0.7-v p-p ) cin delay (ps) p1 (v) p2 (v) p3 (v) comments +29 0.350 0.343 0.443 maximum delay for er <10 -10 0 0.383 0.340 0.443 center of phase margin -29 0.424 0.342 0.443 minimum delay for er <10 -10 input 1 input 2 output
CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC n ghdd4414 n 19 oki semiconductor phase detection between signal and clock at 10 gbps timing -270 -180 -90 0 90 180 270 200 250 300 350 400 output voltage of pd (mv) p1[mv] p2[mv] p3[mv] error free range phase variation (degree) data clock 200mv/div 25ps/div
n ghdd4414 n CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 20 oki semiconductor
oki semiconductor the information contained herein can change without notice owing to product and/or technical improvements. please make sure before using the product that the information you are referring to is up-to-date. the outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. when you actually plan to use the product, please ensure that the outside conditions are reflec ted in the actual circuit and assembly designs. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, b ut not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in con nection with the use of product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringemen t of a third party's right which may result from the use thereof. when designing your product, please use our product below the specified maximum ratings and within the specified operating rang es, including but not limited to operating voltage, power dissipation, and operating temperature. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,of fice automation, communication equipment, measurement equipment, consumer electronics, etc.).these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medica l, including life support and maintenance. certain parts in this document may need governmental approval before they can be exported to certain countries. the purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. copyright 1999 oki semiconductor oki semiconductor reserves the right to make changes in specifications at anytime and without notice. this information furnishe d by oki semiconductor in this publication is believed to be accurate and reliable. however, no responsibility is assumed by oki semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. no lic ense is granted under any patents or patent rights of oki.
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